1. Technical Field
The present invention relates to on-chip diagnostics and testability, and in particular, to phase-locked loop circuits with jitter measurement.
2. Description of the Related Art
As technology advances, predicting the behavior of transistor devices and passive elements such as resistors and capacitors becomes increasingly difficult. Increased uncertainty in the modeling of these devices sometimes mandates integrated circuit designs to function beyond original targets in order to provide enough performance margin over process, voltage, and temperature (PVT) variations. Conservative designs may often result in more power and area consumption than is needed.
If internal system parameters can be measured and used to adjust the system parameters, the system design margin can be greatly enhanced. In the past, system diagnostics were performed by measuring available off-chip test nodes. However, an external diagnostic path is slow, and solutions are not always found. Furthermore, the limited off-chip visibility of internal analog/digital waveforms results in limited learning rates for yield. Hence, the demand for on-chip testability and diagnostics has greatly increased.
In phase-locked loop (PLL) design, key PLL parameters such as jitter, static phase error, and control voltage range are extremely difficult to evaluate in integrated systems. Among these, measuring jitter performance is very challenging, as timing uncertainty in clock generation increases with modern technology.
Jitter measurement methods may detect timing metastability in a large set of latches. By deploying the large set of latches and delay lines, timing uncertainty in a zero-time crossing of some latches could be detected. However, a large number of delay lines could induce additional jitter generation, possibly degrading jitter measurement performance. For example, an instantaneous fluctuation of the supply voltage caused by on-chip digital switching circuits can prevent the short-term jitter measurement from being reliably performed. Also, jitter measurements using an analog charge pump are not favorable due to mismatch requirements of transistors.
On the other hand, a long-term jitter measurement is more immune to instantaneous on-chip variations and provides a more reliable way of evaluating system performance. In accordance with present embodiments, an illustrative method focuses on phase-locked loop (PLL) circuits, thus simplifying hardware complexity by using information already present in the PLL. A monitor circuit operates by measuring a phase error at each reference clock cycle with a programmable error-detection threshold and saves the information in latches for post processing.
An illustrative circuit in accordance with the present principles employs an all-digital instantaneous phase error detector (IPED) and detects peak phase error amplitude only instead of measuring metastability in the zero-time crossing. This makes it possible to make use of relatively simple lumped delay lines. Further, the hardware complexity does not depend on a voltage controlled oscillator (VCO) frequency since the hardware detects phase error amplitude at the phase-frequency detector (PFD) output.
An apparatus includes a phase-locked loop (PLL) circuit including a phase-frequency detector configured to output phase error signals. A phase error monitor circuit is configured to determine instantaneous peak phase error by logically combining the phase error signals and comparing pulse widths of the logically combined phase error signals to a programmable delay time at each reference clock cycle to determine instantaneous phase error change. A storage element is configured to store the instantaneous phase error change.
Another apparatus includes a phase-locked loop (PLL) circuit including a phase-frequency detector configured to output phase error signals. A phase error monitor circuit is configured to determine instantaneous peak phase error. The phase error monitor circuit includes an exclusive OR gate configured to logically combine the phase error signals to provide a first output signal, and a programmable delay line configured to provide a delay time to the first output signal as a threshold against which instantaneous phase error change of the output signal is measured at each reference clock cycle. A storage element is configured to store the instantaneous phase error change.
Yet another apparatus includes a phase-locked loop (PLL) circuit including a phase-frequency detector configured to output phase error signals, and a phase error monitor circuit configured to determine peak instantaneous phase error by logically combining the phase error signals and comparing pulse widths of the logically combined phase error signals to a programmable delay time at each reference clock cycle to determine instantaneous phase error change. The instantaneous phase error change includes a difference signal and a raw signal. A multiplexer is configured to receive as inputs and select one of the difference signal and the raw signal. An accumulator is coupled to an output of the multiplexer to accumulate instantaneous phase error change counts associated with a time window.
Yet another apparatus includes a phase-locked loop (PLL) circuit including a phase-frequency detector configured to output phase error signals, and a phase error monitor circuit configured to determine peak instantaneous phase error by logically combining the phase error signals and comparing pulse widths of the logically combined phase error signals to a programmable delay time at each reference clock cycle to determine instantaneous phase error change. The instantaneous phase error change includes a first signal and a differential signal. A multiplexer is configured to receive as inputs and select one of the first signal and the differential signal. A plurality of counters is coupled to an output of the multiplexer to accumulate instantaneous phase error change counts associated a plurality of instantaneous phase error thresholds such that phase error amplitudes and times are provided to create a jitter histogram.
An apparatus for short-term jitter measurement includes a plurality of programmable delay stages configured to permit selection of a different amount of delay for a clock signal to provide a delayed clock signal for adjustable short-term measurement of jitter movement. A phase detector includes as inputs the clock signal and the delayed clock signal. The phase detector includes a phase-frequency detector configured to output phase error signals. A phase error monitor circuit is configured to determine peak instantaneous phase error change by logically combining the phase error signals and comparing pulse widths of the logically combined phase error signals to a programmable delay time at each reference clock cycle to determine the instantaneous phase error change.
These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.